Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years in the trenches of timing closure, and you know the difference between a design that meets timing on paper and one that actually tapes out without surprises. You understand that the hardest timing problems are usually architectural decisions made months earlier, and you are the engineer who spots those issues during constraint development, not at signoff. You think in clock domains, corner cases, and constraint dependencies. When someone says "it's a timing issue," you already have three hypotheses about where to look.
You are comfortable sitting with RTL designers who want to know why their block won't close, then walking over to the physical implementation team to explain what needs to change in floorplanning. You do not wait for perfect netlists or complete constraints. You work with what you have, flag what is missing, and keep the flow moving. You write scripts because manual checks do not scale, and you have learned that good automation is the difference between closing timing in two weeks versus two months.
At Synopsys, you will work on real SoCs with complex clocking architectures, multiple power domains, and timing challenges that require both technical depth and cross-team collaboration.
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Own synthesis and timing closure for blocks, subsystems, or full SoC designs from RTL handoff through timing signoff
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Develop, validate, and debug SDC timing constraints for multi-mode, multi-corner scenarios across complex clocking architectures
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Perform input and output deliverable sanity checks including constraints analysis, LDRC, logical equivalence checking, and low-power verification at RTL and netlist levels
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Work directly with RTL design, DFT, and physical implementation teams to resolve timing violations, optimize paths, and meet performance targets
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Lead timing-related technical discussions at the block, subsystem, or SoC level, translating design goals into actionable timing strategies
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Automate checks, flows, and reporting using TCL, Perl, or Python to improve efficiency and reduce manual errors
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Debug and resolve timing closure challenges using Synopsys Fusion Compiler and PrimeTime, analyzing timing paths, clock skew, and setup/hold violations
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Enable SoC tapeouts by ensuring timing closure happens on schedule without last-minute surprises or re-spins
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Reduce timing closure iteration cycles by catching constraint issues, clocking problems, and architectural bottlenecks early in the flow
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Improve design quality by ensuring low-power checks, logical equivalence, and timing sanity are validated before handoff to physical implementation
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Accelerate team productivity by building automation that scales across multiple blocks and reduces manual verification overhead
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Influence design decisions upstream by providing timing feedback that shapes RTL architecture, clocking strategy, and DFT insertion
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Strengthen cross-functional collaboration by serving as the technical bridge between RTL, DFT, and physical design teams
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Contribute to the success of complex, high-performance SoC projects that power next-generation AI and semiconductor products
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Bachelor's or Master's degree in IC Design, Semiconductor Engineering, Electrical Engineering, or related field
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0~5+ years of hands-on experience in digital design, timing closure, or SoC implementation
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Proven experience performing multi-mode, multi-corner timing closure of complex blocks, subsystems, or SoCs from synthesis through timing signoff
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Strong expertise in SDC constraint development, validation, and debugging for various modes and corner cases
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Proficiency with Synopsys Fusion Compiler and PrimeTime for synthesis, timing analysis, and signoff
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Solid scripting skills in TCL, Perl, or Python for automation and flow development
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Experience with low-power concepts (UPF) and performing low-power checks at RTL and netlist levels, plus experience with logical equivalence checking and formal verification tools
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You can look at a timing report with 500 violations and quickly identify the three root causes that matter most
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You explain timing closure tradeoffs to RTL designers in terms they understand, and you push back when a proposed fix will create downstream problems
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You write scripts that others on the team actually use because they solve real problems and are easy to maintain
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You stay organized across multiple blocks, modes, and corner scenarios without losing track of what needs to close when
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You are comfortable working across time zones with global teams in RTL, DFT, and physical design, keeping everyone aligned on timing goals
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You do not treat timing closure as a checklist, you treat it as a technical problem that requires judgment, collaboration, and sometimes creative solutions
