Rebellions is the first company in the world to productize a UCIe-based die-to-die (D2D) interconnect for AI accelerator, stitching multiple NPU dies into a single chiplet system. As an HSIO Interconnect Subsystem RTL Design Engineer, you will own the RTL of the subsystems that move data between
dies — the communication backbone of the chiplet system — rather than the AI compute die itself. You will work side-by-side with the interconnect architect to concretize the microarchitecture of our next-generation D2D subsystem and carry it from spec to working silicon.
Your immediate focus is D2D; over time, the same subsystem-design skills open the door to other
high-speed interconnects across the HSIO roadmap.
- Subsystem RTL Design: design and implement the D2D interconnect subsystem - transaction management and datapath, link-level reliability (retry/replay, CRC, FEC), and built-in test, debug, and monitoring structures (traffic generation/comparison, loopback, per-port counters, performance monitors)
- NPU SoC System Understanding: work with a system-level view of the NPU SoC — the D2D subsystem exists to carry accelerator traffic, so understanding how compute, memory hierarchy, and NoC move data (and what bandwidth, latency, and ordering they demand of the interconnect) is essential to getting the microarchitecture right
- Microarchitecture Definition: concretize the subsystem microarchitecture together with the architect - including the areas that industry specs leave under-defined
- Standard-Spec-Based Design: design against open standards(UCIe, CHI, CHI C2C and related specs) and integrate vendor controller/PHY IP through standard interfaces (e.g., RDI/FDI/AXI) and RBLN in-house NoC interface
- Cross-Functional Collaboration: partner with verification, SoC integration, firmware(register map / control interface), and PSI teams to make the subsystem work in the real system
- Silicon Bring-up: participate in D2D link bring-up and support post-silicon debugging down to RTL simulation when issues go deep
- 6–8 years of combined experience in RTL design using SystemVerilog/Verilog (M.S. counted as 2 years, Ph.D. as 4 years toward this total)
- Full Design Lifecycle: proven experience from architecture definition through RTL implementation, tape-out, and silicon bring-up
- Simulation & Debugging: proficiency in logic simulation tools (VCS, Xcelium) with the ability to resolve complex RTL issues
- Quality Toolchain: experience with industry-standard quality flows, including Lint, CDC, DFT, and Synthesis
- Communication & collaboration: strong, collaborative cross-functional work — root-causing a chiplet issue spans architecture, verification, firmware, PSI, and vendor teams, so we value engineers who debug with data rather than blame and own their mistakes honestly
- Design-for-Debug: building testability and observability into silicon (loopback modes, traffic generators, counters, performance/error monitors)
- Transaction Ordering: outstanding-transaction management, ordering rules, and flow control in AMBA/NoC-based systems
- Vendor IP Integration: integrating third-party controller/PHY IP through standard interfaces (RDI/FDI, PIPE, or similar)
- IP Design in Other Domains: end-to-end RTL ownership of a non-interconnect IP block (e.g., memory controller, DMA engine, codec, sensor interface) — we value depth of design experience over the specific protocol you've worked on
- High-Speed Link Design: hands-on design experience at the link layer or protocol layer of a high-speed interface (e.g., PCIe, CXL, Ethernet, or a proprietary die-to-die/chip-to-chip link)
- SerDes / high-speed PHY: working understanding of SerDes-based high-speed links — PCS/PMA partitioning, equalization, clock/data recovery, and link training — and the digital logic that interfaces to a SerDes PHY
- D2D architecture, from spec to silicon: you will work daily with the interconnect architect on next-generation D2D architecture, and experience standard-spec-based design at a company that actually ships it — from an evolving industry spec all the way to productized silicon
- Beyond D2D: as the HSIO roadmap expands, you can grow into subsystem design for other high-speed IO domains — Ethernet, optical interconnect, and whatever comes next
Note: this role centers on interconnect and communication subsystems. If you enjoy making dies talk to each other reliably at high speed — rather than building the compute die itself — this is the seat. Prior high-speed IO IP design experience is not required: solid IP design experience in another domain, combined with any of the Preferred Qualifications above, is a strong basis to apply.
전형절차
- 서류전형 > On-line 인터뷰 > On-site 인터뷰 > Culture-fit 인터뷰 > 처우 협의 > 최종 합격
- 전형절차는 직무별로 다르게 운영될 수 있으며, 일정 및 상황에 따라 변동될 수 있습니다.
- 전형 일정 및 결과는 지원 시 작성하신 이메일로 개별 안내드립니다.
참고사항
- 본 공고는 모집 완료 시 조기 마감될 수 있습니다.
- 지원서 내용 중 허위사실이 있는 경우에는 합격이 취소될 수 있습니다.
- 채용 및 업무 수행과 관련하여 요구되는 법령 상 자격이 갖추어지지 않은 경우 채용이 제한될 수 있습니다.
- 보훈 대상자 및 장애인 여부는 채용 과정에서 어떠한 불이익도 미치지 않습니다.
- 담당 업무 범위는 후보자의 전반적인 경력과 경험 등 제반사정을 고려하여 변경될 수 있습니다. 이러한 변경이 필요할 경우, 최종 합격 통지 전 적절한 시기에 후보자와 커뮤니케이션 될 예정입니다.
- 채용 관련 문의사항은 아래 메일 주소로 문의바랍니다.
- [email protected]
